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Processing-in-memory (PIM) architectures attempt to overcome the von Neumann bottleneck by combining computation and storage logic into a single component. The content-addressable parallel processing paradigm (CAPP) from the seventies is an in-situ PIM architecture that leverages content-addressable memories to realize bit-serial arithmetic and logic operations, via sequences of search and update operations over multiple memory rows in parallel. In this paper, we set out to investigate whether the concepts behind classic CAPP can be used successfully to build an entirely CMOS-based, general-purpose microarchitecture that can deliver manyfold speedups while remaining highly programmable. We conduct a full-stack design of a Content-Addressable Processing Engine (CAPE), built out of dense push-rule 6T SRAM arrays. CAPE is programmable using the RISC-V ISA with standard vector extensions. Our experiments show that CAPE achieves an average speedup of 14 (up to 254) over an area-equivalent (slightly under 9mm^2 at 7nm) out-of-order processor core with three levels of caches. 

This work proposes a new Ferroelectric FET (FeFET) based Ternary Content Addressable Memory (TCAM) with features of integrated search and read operations (along with write), which we refer to as TCAM-RAM. The proposed memory exploits the unique features of the emerging FeFET technology, such as 3-terminal device design, storage in the gate stack, etc., to achieve the proposed functionality. We also introduce Approximate CAM-RAM, which can quantize the bit vector similarity. All the proposed designs operate without negative voltages. We describe both NAND and NOR variants of CAM design. Our CAM design provides 31% area improvement over the previous FeFET 6T CAM design.